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积优芯电子科技(上海)有限公司招聘简章
2017-06-17 17:01     (点击次数:)

公司性质:外资企业

联系人:殷莺

公司行业:软件和信息技术服务业

联系电话:021-33665868

公司规模:150-500

电子邮箱:shadow.yin@guc-asic.com yj.xiao@guc-asic.com 

工作城市:上海市、南京市

积优芯电子科技(上海)有限公司为创意电子股份有限公司投资设立之全资子公司,于2009年在上海注册成立。

创意电子为全球通讯、计算机和消费性电子公司所仰赖的首屈一指的ASIC设计服务公司,拥有全球最先进90nm65nm40nm 28nm16nm的纳米系统单芯片(SoC)设计经验和提供全方位解决方案,包括各类数字、模拟及CPU核等IP,系统开发及验证平台,封装测试设计与服务。       

创意电子成立于公元 1998 年,已在台湾证券交易所公开上市,股票代号为3443。公元 2003 年,全球晶圆代工服务的领导厂商——台湾集成电路制造股份有限公司 (以下简称台积电,TSMC) 始参与投资创意电子,且成为目前最大之投资股东。 

创意电子与台积电(TSMC) 策略联盟,可提供更先进、更完整及更优质的IC设计服务及解决方案,服务的客户群及合作伙伴遍布全球,包括大中华区、日本、韩国、北美及欧洲等地。2015年营收超过二亿四千万美金。

招募对象为2017年应届本科及以上学历。

招募职位及相关要求:

 1. Front-end design engineer (FE Job Description)  ASIC设计前端工程师(综合/时序/功耗)

    - Logic/physical Synthesis
    - Design (RTL coding/netlist) quality check
    - Timing constraints (SDC) creation, validation, and quality check, timing budget

    - STA/SI timing closure flow with Synopsys tools
    - Co-work with BE team to implement chip partition, floorplan and final timing closure on block/chip level design
    - Achieve special timing closure, such as DDR/eMMC/SDIO etc. IO design

    - Low power file (UPF/CPF) creation, validation and quality check with synopsys MVRC/Conformal-CLP

    - Power analysis/verification with UPF/CPF flow
    - Enhance current timing/low power design closure flow from front-end to back-end

    Candidate requirements:
    - BSEE/ME/CE, MSEE/ME/CE is preferred (电子工程/微电子/通讯工程)
    - Interest in IC design implementation
    - Hand-on experience in Synopsys (DC/PT/Formality/MVRC) and Cadence (LEC/LEC-CLP) is preferred
    - Users of Perl or TCL is preferred
    - English communication skill

  2. BE design engineer (BE Job Description) ASIC设计后端布局布线工程师

    - Block/Chip level physical design implementations from netlist to GDSII flow
    - Design/IP Macro/IO floorplaning
    - Power design, analysis & IRDrop signoff

    - Clock distribution analysis and CTS generation
    - Place & routing, timing closure and timing signoff
    - Physical design verification (DRC/LVS/ERC/DFM)

    - UPF/CPF design flow implementation

    Candidate requirements:
    - BSEE/ME/CE, MSEE/ME/CE is preferred (电子工程/微电子/通讯工程)
    - Interest in IC design implementation
    - Hand-on experience in Synopsys (ICC/ICC2/PT/StarRC) and Cadence (EDI/EPS) is preferred
    - User of Perl or TCL is preferred
    - English communication skill

    3.DFT design engineer (DFT Job Description) ASIC可测性设计工程师

    - Block/Chip level DFT feature and architecture definition
    - DFT specification generation and review with customer co-work
    - Implement block/chip level DC/AC SCAN, BSD, MBIST and IP macro test

    - Do all verifications on DFT structures, and deliver quality production ATE patterns

    - Deliver quality DFT timing constraints and support BE team timing closure

    - Support ATE bring-up, and debug the ATE patterns for production flow
    - Support logic scan/MBIST etc. DFT diagnosis for yield improvement

    Candidate requirements:
    - BSEE/ME/CE, MSEE/ME/CE is preferred (电子工程/微电子/通讯工程)
    - Interest in IC design implementation
    - Hand-on experience in Synopsys (DFT Compiler/TetraMax/VCS) and Mentor Tessent MBIST is preferred
    - User of Perl or TCL is preferred
    - English communication skill

应聘流程:

投递简历->电话通知面试->面试->3方协议签署-〉提前实习培训

投递个人简历至邮箱:shadow.yin@guc-asic.com  yj.xiao@guc-asic.com 

工作地点:上海、南京市

联系电话:021-33665868

公司网址信息:www.guc-asic.com

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